Publications

1. Ho, C. Lau, G. Hills, M.M. Shulaker “Carbon Nanotube CMOS Analog Circuitry,” IEEE Transactions on Nanotechnology (TNANO), 2019: 1-4.**
2. P.S. Kanhaiya, Y. Stein, W. Lu, J.A. del Alamo, M.M. Shulaker “X3D: Heterogeneous Monolithic 3D Integration of “X”(Arbitrary) Nanowires: Silicon, III–V, and Carbon Nanotubes” IEEE Transactions on Nanotechnology (TNANO) 18 (2019): 270-273. Print. **
3. M.S. Aly, T.F. Wu, A. Bartolo, Y.H. Malviya, W. Hwang, G. Hills, I. Markov, M. Wootters, M.M. Shulaker, H.S.P. Wong, S. Mitra “Nonsilicon, non-Von Neumann Computing—PART I,” Proceedings of the IEEE 107.1 (2018): 19-48. Print.
4. Srimani, G. Hills, M.D. Bishop, M.M. Shulaker “30-nm Contacted Gate Pitch Back-Gate Carbon Nanotube FETs for Sub-3-nm Nodes” IEEE Transactions on Nanotechnology (TNANO) 18 (2018): 132-138. Print. **
5. Lau, T. Srimani, M. D. Bishop, G. Hills, M. M. Shulaker “Tunable n -Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfO X Films” ACS Nano [19360851] 12.11 (2018): 10924-10931. Print. **
6. Hills, M. G. Bardon, G. Doornbos, D. Yakimets, P. Schuddinck, R. Baert, D. Jang, L. Mattii, S. M. Sherazi, …, M. M. Shulaker, et al. “Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI” IEEE Transactions on Nanotechnology [1536125X] 17.6 (2018): 1259-1269. Print.
7. S. Kanhaiya, G. Hills, D. A. Antoniadis, M. M. Shulaker “DISC-FETs: Dual Independent Stacked Channel Field-Effect Transistors” IEEE Electron Device Letters [07413106] 39.8 (2018): 1250-1253. Print. **
8. Srimani, G. Hills, M. D. Bishop, U. Radhakrishna, A. Zubair, R. S. Park, Y. Stein, T. Palacios, D. Antoniadis, M. M. Shulaker “Negative Capacitance Carbon Nanotube FETs” IEEE Electron Device Letters [07413106] 39.2 (2018): 304-307. Print. **
9. F. Wu, H. Li, P. Huang, A. Rahimi, G. Hills, B. Hodson, W. Hwang, J. M. Rabaey, H. S. Wong, M. Shulaker, et al. “Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration” IEEE Journal of Solid-State Circuits [00189200] 53.11 (2018): 3183-3196. Print.
10. M. Shulaker, G. Hills, R. S. Park, R. T. Howe, K. Saraswat, H. S. Wong, S. Mitra “Three- Dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip” Nature [00280836] 547.7661 (2017): 74-78. Print.
11. S. Park, G. Hills, J. Sohn, S. Mitra, M. M. Shulaker, H. S. Wong “Hysteresis-Free Carbon Nanotube Field-Effect Transistors” ACS Nano [19360851] 11.5 (2017): 4785-4791. Print. May 2017
12. S. Park, M. M. Shulaker, G. Hills, L. Suriyasena Liyanage, S. Lee, A. Tang, S. Mitra, H. S. Wong “Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution” ACS Nano [19360851] 10.4 (2016): 4599-4608. Print.
13. Shulaker, H. S. Wong, S. Mitra “Computing with Carbon Nanotubes” IEEE Spectrum [00189235] 53.7 (2016): 26-52. Print.
14. Gielen, J. Van Rethy, J. Marin, M. M. Shulaker, G. Hills, H. S. Wong, S. Mitra “Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies” IEEE Transactions on Circuits and Systems I: Regular Papers [15498328] 63.5 (2016): 577-586. Print.
15. Hills, J. Zhang, M. M. Shulaker, H. Wei, C. Lee, A. Balasingam, H. P. Wong, S. Mitra “Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems [02780070] 34.7 (2015): 1082-1095. Print.

Rigorously Refereed Conferences:

1. Srimani, G. Hills, C. Lau, M.M. Shulaker “Monolithic Three-Dimensional Imaging System: Carbon Nanotube Computing Circuitry Integrated Directly Over Silicon Imager” Symposium on VLSI Technology (VLSI-Technology) : Digest of Conference. (2019):1-2. Print. **
2. Kanhaiya, C. Lau, G. Hills, M. Bishop, M.M. Shulaker “1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS” Symposium on VLSI Technology (VLSI-Technology) : Digest of Conference. (2019):1-2. Print. **
3. A.G. Amer, R. Ho, G. Hills, A.P. Chandrakasan, M.M. Shulaker “SHARC: Self-Healing Analog with RRAM and CNFETs,” IEEE International Solid-State Circuits Conference (ISSCC). 2019: 470-472. Print. **
4. M. Sabry Aly, T. F. Wu, A. Bartolo, Y. H. Malviya, W. Hwang, G. Hills, I. Markov, M. Wootters, M. Shulaker, H. S. Philip Wong, et al. “The N3XT Approach to Energy-Efficient Abundant-Data Computing” Proceedings of the IEEE [00189219] 107.1 (2019): 19-48. Print.
5. Hills, D. Bankman, B. Moons, L. Yang, J. Hillard, A. Kahng, R. Park, M. Verhelst, B. Murmann, M. Shulaker, et al. “TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs” ACM/ESDA/IEEE Design Automation Conference (DAC) . (2018): 1-10. Print.
6. F. Wu, H. Li, P. Huang, A. Rahimi, J. M. Rabaey, H. S. Wong, M. M. Shulaker, S. Mitra “Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study” IEEE International Solid-State Circuits Conference (ISSCC) . (2018): 492-Print.
7. Hills, M. M. Shulaker, H. S. Wong, S. Mitra, D. Bankman, B. Moons, L. Yang, J. Hillard, A. Kahng, Park, et al. “TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration using Carbon Nanotube FETs” Design Automation Conference – DAC . (2018): 1-10. Print.
8. M. Shulaker, G. Hills, H. S. Wong, S. Mitra “Transforming Nanodevices to Next Generation Nanosystems” International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) . (2016): 288-292. Print.